Next-generation Compute Devices, Programmable Logic (FPGA), Graphics units, (also called Compute Devices) and data centers are trending toward systems providing greater computational capabilities, operational flexibility, and improved power efficiency. The combination of demands presented by next-generation data centers and Compute devices present significant challenges for current general-purpose servers. Increasing demand for reduced system complexity, business agility and scalability has increased demand for virtualized data center infrastructure that will place additional demands on next-generation data servers. To meet such varied requirements, next-generation servers may be designed to address a specific workload matrix. However, such task- or service-oriented design, while improving power efficiency, compromises the long term flexibility of such next-generation servers. Thus, the servers used in next-generation data centers must be capable of providing a cost effective solution that addresses current and future computational demands, provide a flexible platform capable of meeting evolving operational needs, while delivering improved power efficiency over legacy servers.
The challenges presented by the growing ubiquity of Internet-of-Things (IoT) devices are surprisingly similar to those presented by next-generation data centers. With literally billions of connected devices, cloud-based infrastructure must quickly evaluate high-bandwidth data streams and determine which data may be processed and which data may be safely dropped.
Next-generation platforms share several distinct requirements: increased bandwidth; increased flexibility to promote increased functionality; improved power efficiency (or reduced power consumption) and reduced footprint requirements. Heretofore, designers may address such varied demands by packing additional components on a standard printed circuit board. The limitations inherent in such single board solutions may not satisfactorily address the multiple demands placed on next-generation devices. Such limitations include: chip-to-chip bandwidth limitations based on interconnect density; the power demand of long distance traces between chips; and the increased physical size of printed circuit boards to accommodate the chips. Monolithic integration of system components provides a potential solution, however such integration does not readily permit the integration of system components, each of which may evolve at different rates. For example, a logic chip built using a newer technology may not easily integrate or lend itself to monolithic fabrication with a memory chip built using an older technology.
Conventional solutions are therefore unable to meet future demands of higher bandwidth, greater power efficiency, increased functionality, and increased operational flexibility—all in a physically smaller package and die architecture.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications and variations thereof will be apparent to those skilled in the art.